Parity bits have long been used for error detection in the transmission of digital binary signals. The parity bit used can be one of two types, even or odd. In an even parity scheme, the parity bit is defined to be a 1 or 0 so that the number of bits with a value of 1 in the data and parity bits combined is even. In an odd parity scheme this total number of bits is made to be odd. Thus, the odd parity bit would be the complement of the even parity bit. For a data of 10110, the even parity bit is 1. The even parity bit may be obtained by XORing all the data bits. Thus, 1 XOR 0 XOR 1 XOR 1 XOR 0 would equal 1. Obtaining the complement of this value would be the odd parity.
A parity bit of the data bits to be transmitted is typically computed at a sending end. The resultant parity bit is transmitted to a receiving end along with the data bits. The parity bit may be transmitted on the same channel as the data or using a separate channel. Within a computer system, a separate bit line is generally used to transmit the parity bit to enhance performance.
The receiving end checks the data received and verifies that the parity bit generated from this data is consistent with the parity bit that was generated at the sending end. If the parity bit generated is not consistent with the parity bit received from the sending end, transmission error is determined to have occurred. This provides limited error detection capabilities.
Typical prior art parity generators have been built using 2-bit XOR cells based on CMOS technology. A 2-bit XOR cell accepts two bits on the input line and generates the XOR of the two bits on the output line. A parity generator for generating parity bit for eight input bits is shown in FIG. 1. The parity generator comprises of seven 2-bit XOR cells disposed in three rows. Four cells 101-104 are disposed in a first row. Each of these cells (ex. 102) accepts two input bits (ex. 110, 111 for the cell 102) and generates XOR of these bits on the corresponding output line (Ex. 117). The input lines of cell in the subsequent stages are coupled to output lines of the cells in the previous stage. Thus each of these blocks are cascaded to the next stage. The output 122 of the 2-bit XOR cell 107 in the last stage will be the XOR of all the input bits on input lines 108-115. The parity bit for eight (2.sup.3) bits is generated in three delay stages. In general, a parity generator with 2.sup.n inputs would require n delay stages. Delay of this magnitude is not acceptable to the high performance microprocessors that use wider bus bandwidth and high clock speeds. What is required is a high-speed parity generator that computes the parity bit in lesser number of delay stages and thus in lesser amount delay-time.